1. Field
The present invention relates to a channel device and an information processing apparatus having the channel device and a method thereof.
2. Description of the Related Art
An improvement in transferring data distributed to multiple areas in a memory to an input-output (IO) device is needed. For example, there has been a system that is capable of transferring data stored on a hard disk to an arbitrary external device by direct memory Access (DMA).
Another data transfer method is a chain data processing. The chain data processing is a method for transferring data distributed to the multiple areas in the memory to the IO device in accordance with one command.
The channel device controls and executes the data transfer between the IO device by fetching a command for controlling the data transfer from the memory. The command includes a data address in the memory, a transfer byte count and a flag that are used by the channel device for the data transfer. Data addresses and byte counts of successive information are designated by setting a chain data flag from among flags included in command where the data to be read or written are distributed to the multiple areas in the memory in transferring data between the IO device and the memory. The process disclosed above is generally referred to as the chain data processing and the data transferred successively by the chain data processing is referred to as chain data.
FIG. 9 illustrates a transfer method used of a conventional channel device for transferring data using the chain data processing.
FIG. 9 illustrates a case in which data stored in the memory is transferred to the IO device connected with the information processor through the channel device.
In FIG. 9, channel command word (CCW) columns are provided in the memory incorporated in the information processor before transferring the data by the chain data processing.
The CCW columns associates the first addresses (DTA 0, DTA 1 and DTA 2) of data distributed to the multiple data areas (data 0, data 1 and data 2) with transfer volumes of the data, i.e., transfer data lengths of each data, LNG 0, LNG 1 and LNG 2) and stores the first addresses and the data transfer amount.
An IO control area stores channel command word addresses (CCWAs) indicating addresses of the CCW columns in the memory. When an IO command is issued to transfer the data stored in the memory, the channel device reads the first address of the CCW column according to a designated CCWA. The channel device: (1) issues a command for transferring the data to a destination IO device to notify a direction of the data transfer and a amount of the data transfer; (2) reads first data 0 from the memory according to a data transfer start address, DTA 0 and a data transfer amount, LNG 0, stored in one of the CCW columns and then transfers the data to the IO device. After the data transfer according to the first CCW is completed, the next CCW is read.
Then the channel device: (3) issues a command for transferring the chain data to the IO device; (4) transfers the data read from the memory according to an address (DTA 1) and a transfer amount (LNG 1) stored in the next CCW column to the IO device.
As disclosed above, the channel device continues to issue the commands for transferring the chain data and transfers the chain data until all the chain data are transferred (5, 6).
FIG. 9 illustrates an operation of a write command, i.e., the data transfer from the memory to the IO device. An operation on a read commend, i.e., the data transfer from the IO device to the memory, is basically the same as the operation in FIG. 9 except the data is transferred in a reverse direction.
FIG. 10 illustrates the structure of the channel device implementing the chain data disclosed above. The channel device 100 shown in FIG. 10 has a PCI bus controller 110, a channel controller 120, a data transfer controller 130 and an IO controller 140.
PCI bus controller 110 controls a connection with a PCI bus included in the information processing apparatus. Channel controller 120 controls the entire operation of the channel device 100. Data transfer controller 130 controls data exchange between the memory included in the information processing apparatus and the IO device. The IO controller 140 controls a connection with the IO interface included in the IO device.
The data transfer controller 130 has CCW controller 131, transfer controller 132, memory transfer controller 133, data buffer unit 134 and IO transfer controller 135.
CCW controller 131 controls the operations of the information processing apparatus relating to the CCW such as reading data from the CCW columns in processing the chain data. Transfer controller 132 controls the entire operation of the data transfer controller 130. Memory transfer controller 133 receives data stored in the memory through PCI bus controller 110 and writes the data in data buffer 134 or transfers the data stored in data buffer 134 to the memory through PCI bus controller 110.
Data buffer unit 134 compensates for a difference between rates of transmissions from the memory and from the IO device. IO transfer controller 135 transfers data stored in data buffer unit 134 to the IO device through the IO controller 140 or writes data sent from the IO device in data buffer unit 134.